For 20 nm devices and beyond, device performance significantly relies on middle-of-the-line (MOL) processes due to contact resistance and gate to trench silicide (active area contact) capacitance issues. Due to the limited process margin with a small gate pitch, the trench silicide formation is very challenging. In particular, the trench etch is affected by embedded silicon germanium (eSiGe) and raised source/drain regions and cap oxide thickness. To insure that the trench is open, an over-etch may be used, but that generates source/drain gouging (in which the source/drain silicon is consumed). The subsequent silicide will then be formed deep into the junction area, which causes unwanted junction leakage (by diffusing horizontally) and silicide piping (by diffusing vertically along the current path and touching the junction). If the trench over-etch is reduced, the trench may not be open sufficiently to form the silicide. In both cases, yield is lost.
A need therefore exists for methodology enabling formation of trench silicide with reduced junction leakage and silicide piping, and the resulting device.